ARINC818 controller Transmitter and Receiver IP core

Overview

ARINC-818 standard support with 1GFC, 2GFC and 4GFC speeds.
Built-in hierarchical interrupt controller with multiple interrupts from one source tracking.
Built-in DMA engine.
Standard 64-bits AMBA 3 AXI Master and APB slave interfaces.
Big and little endian data support.

FC frames processing: SOF and EOF detection, CRC check, receiver errors detection, FC header decode.
ADVB processing: ADVB containers allocation, errors check, ADVB containers header and Object 0 payload decoding.
Support of all ARINC-818 standard image sizes and formats (except YCbCr).
Built-in image processing support:
Image format conversion to Grayscale:8, RGB:565 or RGB:888 with programmable coefficients;
Image brightness histogram calculation;
Semi-transparent layering partial support (all color components divided by two);
Programmable tables for brightness correction;
Blackening (up to 6 windows);
Image framing.
Configurable error response.
Built-in receiver statistic counters.
RAW data mode grabbing support.

Maturity

Silicon

Availability

Available now