TSMC plans 3-D IC assembly launch early in 2013
Peter Clarke, EETimes
2/2/2012 8:32 AM EST
LONDON – Leading IC foundry Taiwan Semiconductor Manufacturing Co. Ltd. plans to announce 3-D IC assembly service as a general offering at the beginning of 2013, according to Maria Marced, president of TSMC Europe.
The technology is called COWOS internally, standing for chip on wafer on substrate and Marced said the company has one year to get all physical design kits and EDA support in place to allow customers to design with COWOS.
To read the full article, click here
Related Semiconductor IP
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related News
- GUC Announces 2.5D and 3D Multi-Die APT Platform for AI, HPC, Networking ASICs
- Siemens automates 2.5D and 3D IC design-for-test with new Tessent Multi die solution
- The Importance of 3D IC Ecosystem Collaboration
- proteanTecs Joins TSMC 3DFabric™ Alliance, Expanding Its Support of the 3D IC Ecosystem
Latest News
- Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications
- GlobalFoundries and Navitas Semiconductor Partner to Accelerate U.S. GaN Technology and Manufacturing for AI Datacenters and Critical Power Applications
- VLSI EXPERT selects Innatera Spiking Neural Processors to build industry-led neuromorphic talent pool
- SkyWater Technology and Silicon Quantum Computing Team to Advance Hybrid Quantum-Classical Computing
- Dnotitia Revolutionizes AI Storage at SC25: New VDPU Accelerator Delivers Up to 9x Performance Boost