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LPDDR4 IP

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Search (12)
Compare 12 LPDDR4 IP from 7 vendors (1 - 10)
  • LPDDR4x/4 PHY IP for 22nm
    • Compliant for JEDEC standards for LPDDR4x/4 with PHY standards
    • DFI Interface Compliant
    • Supports 1,2, or 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR4x/4 PHY IP for 22nm
  • LPDDR4/3, DDR4/3 Memory Controller IP
    • Compliant with JEDEC standards for LPDDR4/3, DDR4/3
    • DRAM rank of up to 4
    • Lock-step-based controlling of multiple DRAM devices up to x64 DQ width
    • Support for dynamic DRAM frequency scaling
    Block Diagram -- LPDDR4/3, DDR4/3 Memory Controller IP
  • DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 32-bit increment
    Block Diagram -- DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
  • DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 32-bit increment
    Block Diagram -- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
  • DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
    • Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
    • Support x8/x16/x32 DRAM data bus configuration (programmable)
    • Support Multi-Ranks DRAM configuration
    • DDR base on DFI spec 4.0 compliant.
    Block Diagram -- DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
  • LPDDR4X / LPDDR4 Controller
    • Maximizes bus efficiency via Look- Ahead command processing, Bank Management and Auto-Precharge
    • Minimal latency achieved via parameterized pipelining
  • Denali High-Speed DDR PHY for TSMC 22ULP
    • LPDDR4/LPDDR3/DDR4/DDR3/DDR3L training with write-leveling and data-eye training
    • I/O pads with impedance calibration logic and data retention capability
    • Optional clock gating available for low-power control
    • Multiple PLLs for maximum system margin
  • SDRAM LPDDR5/4x/4/3/2 Host Controller & PHY - TSMC 16nm 16FFC,FF
    • DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • Built-in Gate Training, Read/Write Leveling, and VREF Training
    • Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • SDRAM DDRx & LPDDR4x Host Controller & PHY - TSMC 12nm 12FFC,FFC+
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
  • DDRx & LPDDRx DRAM Combo Memory Controller
    • + DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
    • + Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
    • + Built-in Gate Training, Read/Write Leveling, and VREF Training
    • + Multi-Port Configurable AXI4 Interface with QoS Signaling, Single AXI4-Lite Programming Interface
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