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Deskew PLL IP for UMC

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Compare 92 Deskew PLL IP for UMC from 3 vendors (1 - 10)
  • Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
    • Process portable
    • Proven (65nm to 3nm)
    • Full SCAN testable
    • Core voltage supply
  • UMC L65LP 65nm Deskew PLL - 60MHz-300MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L65LP 65nm Deskew PLL - 120MHz-600MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L65LP 65nm Deskew PLL - 240MHz-1200MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L55LP 55nm Deskew PLL - 60MHz-300MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L55LP 55nm Deskew PLL - 120MHz-600MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L55LP 55nm Deskew PLL - 240MHz-1200MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L40LP 40nm Deskew PLL - 75MHz-375MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L40LP 40nm Deskew PLL - 150MHz-750MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • UMC L40LP 40nm Deskew PLL - 300MHz-1500MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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