Hash and HMAC Accelerator IP for TSMC
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Hash and HMAC Accelerator IP
for TSMC
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Hash and HMAC Accelerator IP
for TSMC
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- 7nm
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Poly1305 Crypto Accelerator
- Wide bus interface (128-bit data, 128-bit keys, 135-bit digest) or 32-bit register interface
- Key size: 128 bits
- Includes initialization stage
- Supports continuation mode
- Fully synchronous design
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SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators
- Wide bus interface (1024-bit data, 512-bit digest) or 32 bit register interface
- MD5, SHA-1, SHA-2, SHA-3
- SHA-2/3 in 224/256/384/512 modes
- Message puffing for all algorithms
- Message data scheduling hardware
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SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators
- Wide bus interface
- Supporting HMAC and Basic Hash operations for all algorithms: MD5, SHA-1, SHA-2 (224, 256, 384, 512), SHA-3 (224, 256, 384, 512)
- MAC Key XOR and Message padding
- Message data scheduling hardware
- Calculation of “inner digest” and “outer digest” from a MAC Key input
- Calculation of “inner hash” and “outer hash” from a MAC Key input or “inner digest” and “outer digest” input
