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eMMC PHY IP for TSMC

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Compare 5 eMMC PHY IP for TSMC from 3 vendors (1 - 5)
  • M31 eMMC/SDIO at TSMC 28HPC+ Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 28HPC+ Process
  • M31 eMMC/SDIO at TSMC 22ULP Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 22ULP Process
  • M31 eMMC/SDIO at TSMC 22ULL Process
    • Supports HS400 (400Mbps), HS200 (200Mbps), High-speed DDR (52Mbps) and etc.
    • Consisting of driver, receiver & pull-up/down resistors
    • Power-sequence free
    • Provides multi-driving-strength selection
    Block Diagram -- M31 eMMC/SDIO at TSMC 22ULL Process
  • SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
    • Compliant with eMMC5.1 and SD 6.0
    • Supports 1.2/1.8V and 3.3V bus voltages and all the operating modes for SD 6.0 and eMMC5.1
    • Supports 1.8V signaling for SD 6.0 host–low voltage signaling (LVS)
    • Includes high speed IOs and DLL/delay lines to guarantee alignment between the application processor and memory device
  • eMMC/SDIO/SD
    • Compliant with eMMC5.1 specifications, up to 200MHz
    • Support HS400, HS200, High-Speed DDR, High-Speed SDR, and back compatible with legacy eMMC interface
    • Support Enhanced Strobe in HS400
    • Compliant with SD3.01/SDIO3.00 specifications, up to 208MHz
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