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PCI Express Phy IP for TSMC

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Compare 21 PCI Express Phy IP for TSMC from 4 vendors (1 - 10)
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  • 7nm
  • PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
    • Fully compliant with PCI Express Base 5.0 electrical specifications
    • Compliant with PIPE5.2 (PCIe) specification
    • Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
    Block Diagram -- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
  • PCIe 5.0 PHY, NCS, TSMC N7 x1, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, NCS, TSMC N7 x1, North/South (vertical) poly orientation
  • PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, TSMC7FF G2, x6, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, TSMC7FF G2, x6, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, TSMC7FF G2, x4, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, TSMC7FF G2, x2, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, TSMC7FF G2, x2, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, TSMC7FF G2, x1, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, TSMC7FF G2, x1, North/South (vertical) poly orientation
  • 10G PHY for PCIe 2.0, TSMC 7FF x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- 10G PHY for PCIe 2.0, TSMC 7FF x2, North/South (vertical) poly orientation
  • 10G PHY for PCIe 2.0, TSMC 7FF x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- 10G PHY for PCIe 2.0, TSMC 7FF x1, North/South (vertical) poly orientation
  • PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N7, 1.8V, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x2-lane, RC/EP, TSMC N7, 1.8V, N/S orientation
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