Ethernet IP for TSMC

Compare 6 Ethernet IP for TSMC from 2 vendors (1 - 6)

Filter:

1G Deep Buffering Memory Ethernet Switch IP Core
- Delivers Performance
- Highly Configurable
- Easy to use
- Silicon Agnostic
112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
112G Ethernet PHY in TSMC (N7, N5, N3P)
- Optimized for performance, power, and area
- Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)
- Supports IEEE and OIF standards: IEEE 802.3ck, CEI-112G
- Includes auto-negotiation and link training capabilities – IEEE 802.3 clause 73