UCIe IP for TSMC

Compare 5 UCIe IP for TSMC from 4 vendors (1 - 5)

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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads