Die to Die IP for TSMC

Compare 32 Die to Die IP for TSMC from 7 vendors (1 - 10)

UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Emerging Standard Knowledge
- Flexibly Configurable
- Best in Class PPA
2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- Efficiency
- Composability
- Programmability
UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)
- Data rates of up to 4Gbps per pin
- Self-contained hard macro
- Self-calibrating RX sampling phase and threshold selection
- Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test
Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
- Offers leading performance, power, and area / beachfront per terabit
- Includes 16 lanes of NRZ and PAM-4 transmitters or receivers
- Targeting the OIF XSR standards: CEI-112G and CEI-56G
- Implements robust clock forwarded and embedded clock recovery algorithms for additional flexibility
Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
40G Ultralink D2D PHY for TSMC 7nm
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
40G Ultralink D2D PHY for TSMC 5nm
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
40G Ultralink D2D PHY for TSMC 3nm
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)