MIPI D-PHY IP for Samsung
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MIPI D-PHY IP
for Samsung
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MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI
- 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process
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MIPI DPHY-RX
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Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
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Silicon proven in GlobalFoundries 22FDX process
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Compliant to the MIPI D-PHY spec v1.2
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Lane type:1 clock + 4 data(D0 is bi-dir)
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Support for DPHY Ultra Low Power State
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MIPI DPHY-TX - GlobalFoundries 22FDX process
- Data rate per lane: High-Speed mode 80M~2.5G bps, Low-Power mode 10Mbps
- Silicon proven in GlobalFoundries 22FDX process
- Compliant to the MIPI D-PHY spec v1.2
- Support HiSPi-SLVS TX compatible mode
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MIPI DPHY
- Silicon proven in 22, 28, 55, 110nm from Global Foundries, Samsung and SMIC
- Compliant to the MIPI D-PHY spec v1.1 (SEC28/SMIC55/SMIC110)
- Lane type:1 clock + 4 data, bi-directional
- Built-in self test function
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MIPI DPHY v1.2 TX 4 Lanes - SS 8LPU 1.8V, North/South Poly Orientation for Automotive ASIL B Random, AEC-Q100 Grade 1
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 RX 2 Lanes - SS 8LPU 1.8V, North/South Poly Orientation for Automotive ASIL B Random, AEC-Q100 Grade 1
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 TX 4 Lanes - SS 8LPU 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 RX 4 Lanes - SS 8LPU 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 RX 2 Lanes - SS 8LPU 1.8V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY TRx 28nm
- Samsung Foundry 5nm low power enhanced (LN28LPP) CMOS device technology
- 1.8V±5%, 1.2V±5%,1V±5% power supply
- Fully supports MIPI D-PHY v1.2 HS/LP/ULPS Tx/Rx (Backward Compatible with previous versions)
- Supports 80-2100Mbps in D-PHY HS mode