USB3.1/3.0 PHY & Controller

Overview

Key Features

• Reference Clock:
• 25-300MHz, integer multiple of Serial output
• +/-300ppm frequency stability (<20Gbps)
• Support both SRNS & SRIS mode
• Configurable as reference clock repeater
• Internal PLL:
• Used to drive all PHY transmitters and receivers
• Ring PLL covering 1.0-5Gbps
• Programmable pre-divider & feedback divider
• Initiative SSC or reference clock based passive SSC
• LOCK indication
• Data Transmit:
• Rates supported from 1.0-5 Gbps
• AC coupled
• 50? impedance, internally calibrated
• 200-1100mV differential peak-peak, programmable
• 3 tap pre/post-cursor de-emphasis, programmable
• Programmable Rise/Fall times
• Data Receive:
• AC coupled
• 50? impedance, internally calibrated
• 200-1200mV differential peak-peak
• CTLE, programmable
• DFE, 6-tap programmable
• CDR
• Testing:
• Scan
• BIST with PRBS7/23 and PRBS31 (generator & checker)
• Loopback (near end, far end, on/off-die)
• On-chip scope (eye height & width)
• Analog and digital probe points
• HTOL
• IDDQ
• ESD:
• HBM 2000V, [JEDEC JS-001-2014]
• MM 100V, [JEDEC JESD22-A115C]
• CDM 250V, [JEDEC JESD22-C101F]
• Latch Up:
• +-200mA for IO and 1.5*Vsupply for power rails
• Package:
• Wire bond with careful SI/PI analysis for 8Gbps and below
• Flip-Chip with careful SI/PI analysis for 8Gbps and Up
• Interface with controller:
• PIPE4.3 & 32 bits data bus for USB3.x

Deliverables

• Verilog Sim Behavioral simulation model for the PHY
• Encrypted IO spice netlist for SI evaluation
• Integration Guidelines
• Test Guidelines
• GDSII Layout and layer map for foundry merge
• Place and Route LIB and LEF views for the AFE
• LVS and DRC verification reports

Technical Specifications