Ultra Low Area Frequency Synthesizer PLL (3nm - 90nm)

Overview

Widely programmable frequency synthesizer. Ultra-Low Area and Low Power hard macro with industry leading jitter performance for its power/area class.

Key Features

5MHz up to >800MHz input frequency range
8MHz up to 1.6GHz output frequency range, higher in advanced processes
Tiny footprint (0.015mm^2 in 40nm)
Uses core voltage only
Extremely Low power (<1mW @ 400MHz)
Low jitter: Period Jitter < 1ps RMS
Built-in supply decoupling
Simple digital control interface
Optional Spread Spectrum clock generation capability

Benefits

PLL design is ideal for digital core clocking -- tiny size and core voltage only enables placement anywhere
PLL can be programmed for lowest jitter or lowest power
No external components required
No additional supply decoupling required
Loop automatically adjusts for any input frequency, so no complicated programming is required

Deliverables

GDSII
CDL Netlist (MG Calibre Compatible)
Functional Verilog Model
Liberty timing models (.lib)
LEF
Application Note

Technical Specifications

Foundry, Node

TSMC, GF, SMIC, UMC, Samsung ... 3nm to 90nm

Maturity

Production

Availability

Available Now

GLOBALFOUNDRIES

In Production: 40nm LP

SMIC

In Production: 28nm HK , 28nm PS
Silicon Proven: 28nm HKC+ , 40nm LL

TSMC

In Production: 5nm , 6nm , 7nm , 10nm , 12nm , 16nm , 28nm HPC , 28nm HPCP , 40nm LP , 90nm LP
Pre-Silicon: 28nm LP , 40nm G , 45nm GS , 45nm LP , 90nm G , 90nm GOD , 90nm GT , 90nm zzz
Silicon Proven: 3nm , 4nm , 22nm , 28nm HPM

UMC

In Production: 28nm HLP , 28nm HPC , 40nm LP

Request Info