Ultra High Performance AES-XTS/ECB Core

Overview

The proliferation and expansion of connected devices, connectivity infrastructure, cloud computing, and artificial intelligence is driving for increased need of high-grade security that keeps up with the hyper-connected and hyper-speed technology requirements to protect the significant increase in volume of confidential information and critical data.
AES with Galois/Counter Mode (AES-GCM) is a symmetric cryptographic algorithm that provides a scalable authenticated encryption and data integrity and is used in many applications and security protocols.
The Synopsys Ultra High Performance AES-GCM/CTR IP core implements the AES-GCM/CTR algorithm as specified in the National Institute of Standards and Technology (NIST) Special Publication 800-38D, “Recommendation for Block Cipher Modes of Operation: Galois/Counter Mode (GCM) and GMAC” to achieve terabit performance required for supercomputing applications. It uses the Advanced Encryption Standard (AES) algorithm in counter mode (CTR), and
a high-performance MAC algorithm based on Galois Field multiplication with CTR mode encryption, which can be pipelined for high-throughput operations.

Benefits

  • Supports Terabit performance for supercomputing applications
  • High performance and low latency core with efficient support for varied network traffic
  • Non-stalling architecture
  • Full and interleaved packets
  • Single cycle packets
  • Unique keys/cycle
  • Standards compliant: AES-GCM/GMAC and AES-CTR
  • Customer configurable
  • Scalable architecture
  • 128 to 2048 bits/cycle
  • Up to 2 Tbps @ 1Gz
  • Min 7 cyc data latency
  • Up to 64K contexts
  • Up to 64 GB packet size
  • Encrypt/decrypt/bypass
  • 128/256-bit keys
  • Multi-clock domain: host, secure key port, core
  • NIST FIPS 140-3 security certification ready. Passed NIST CAVP validation
  • Optional support for OSCCA SM4-XTS

Applications

  • High performance compute
  • Networking
  • Smart NICs, switches, routers
  • AI deep learning accelerators
  • Storage
  • MACsec (802.1AE) / IPsec / TLS

Deliverables

  • Verilog HDL
  • Testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Documentation

Technical Specifications

Maturity
Available on request
Availability
Available
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Semiconductor IP