The Cortex-X4 core is a high-performance and low-power product that implements the Arm®v9.2-A architecture. The Arm®v9.2-A architecture extends the architecture defined in the Arm®v8-A architectures up to Arm®v8.7-A.
The Cortex-X4 core is implemented inside a DSU-120 DynamIQ™ cluster. It is connected to the DynamIQ Shared Unit-120 that behaves as a full interconnect with L3 cache and snoop control. This connection configuration is also used in systems with different types of cores where the Cortex-X4 core is the high-performance core.
The following figure shows an example configuration with four Cortex-X4 cores in a DynamIQ™ cluster.
Ultimate Performance for Next-Generation Smartphones and Laptops
Overview
Key Features
- You can use the Cortex-X4 core in a standalone DynamIQ™ configuration where your homogenous DSU-120 DynamIQ™ cluster includes one or more Cortex-X4 cores. You can also use the Cortex-X4 core as the high-performance core in a heterogenous cluster.
- Regardless of the cluster configuration, the Cortex-X4 core always has the same features as described in the following lists.
- Core features
- Implementation of the Arm®v9.2-A A64 instruction set
- AArch64 Execution state at all Exception levels, EL0 to EL3
- Memory Management Unit (MMU)
- 40-bit Physical Address (PA) and 48-bit Virtual Address (VA)
- Generic Interrupt Controller (GIC) CPU interface to connect to an external interrupt Distributor
- Generic Timers interface that supports 64-bit count input from an external system counter
- Implementation of the Reliability, Availability, and Serviceability (RAS) Extension
- Implementation of the Scalable Vector Extension (SVE) with a 128-bit vector length and Scalable Vector Extension 2 (SVE2)
- Integrated execution unit with Advanced Single Instruction Multiple Data (SIMD) and floating-point support
- Activity Monitoring Unit (AMU)
- Support for the optional Cryptographic Extension
- Cache features
- Separate L1 data and instruction caches
- Private, unified data and instruction L2 cache
- Error protection on L1 instruction and data caches, L2 cache, and MMU Translation Cache (MMU TC) with parity or Error Correcting Code (ECC) allowing Single Error Correction and Double Error Detection (SECDED).
- Support for Memory System Resource Partitioning and Monitoring (MPAM)
- Debug features
- Arm®v9.2-A debug logic
- Performance Monitoring Unit (PMU)
- Embedded Trace Extension (ETE)
- TRace Buffer Extension (TRBE)
- Statistical Profiling Extension (SPE)
- Optional Embedded Logic Analyzer (ELA), ELA-600
Benefits
- +15%
- Single-thread performance improvements compared with latest Android flagship smartphones.
- 14 Core Support
- The most advanced and cutting-edge CPU from Arm, designed for increased scalability using “big.LITTLE” CPU configurations for devices from flagship smartphones to laptops.
- Armv9.2
- Industry-leading architecture with the latest security and performance improvements.
Technical Specifications
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