TSN Ethernet Endpoint Controller

Overview

The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC.

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies, and simplifies the development of time-aware applications. While operating autonomously, the TSN-EP provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.

The TSN-EP uses standard AMBA® or Avalon® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide AXI4-Lite or Avalon-MM bus, and packet data are input and output via AXI-Streaming or Avalon ST interfaces with 8-bit data buses.

The TSN-VIP TSN Ethernet Verification IP package is available for this core.

The TSN-EP is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

Key Features

Time Synchronization

Implements IEEE 802.1AS
Grandmaster or Slave functionality
Highly accurate synchronization. Accuracy is typically in the order of few tens ns.
Provides the system with timestamps, periodic event triggers and alarm

Traffic Shaping

Implements IEEE 802.1Qav and IEEE 802.1Qbv
Supports up to 8 traffic classes, as per VLAN (IEEE 802.1Q)
Enables bandwidth reservation and allocation per traffic class, and deterministic, low-latency, low-jitter communication for all traffic classes

Low-Latency Ethernet MAC

Enables high-precision synchronization in TSN networks
Egress latency:
10 Tx clock cycles
Ingress latency:
6 Rx clock cycles
10/100/1000 Mbit/s Ethernet
PHY interfaces: MII, GMII and RGMIII

Easy System Integration

AMBA/AXI4 or Avalon Interfaces
AX4-Lite host interfaces, and AXI4-Stream for packet data
Avalon-MM host interface and Avalon-St for packet-data
Complete reference designs available for Altera and Xilinx, including sample application software
Requires minimal host assistance for its initialization

Verification IP

The TSN-VIP Ethernet Verification IP package is available for this core

Block Diagram

Applications

The TSN-EP is suitable for the implementation of sources of traffic and bridges for TSN Ethernet networks requiring robust, low-latency, and deterministic communication. Such networks are used in automotive, industrial control, and aerospace applications.

Deliverables

The core includes everything required for successful implementation:

Verilog RTL source code or targeted PFGA netlist
Testbenches
Sample Simulation and Synthesis scripts
Comprehensive Documentation
Lightweight PTP stack and device driver for FreeRTOS, easily portable to any other RTOS.
Linux device driver

Technical Specifications

Maturity

Silicon Proven

Availability

Now

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