The Synopsys 1.6T Ethernet PCS IP is based on the IEEE 802.3dj spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications

Overview

Key Features

• The PMA service interface per lane operates with a transfer rate of 106.25Gbps per lane.
• The PCS Client Interface implements a 1600GMII conceptually identical to the 200GMII/400GMII of 802.3 Clause 119.
• The PCS implements Reed-Solomon Forward Error Correction (RS-FEC). The RS-FEC implements the RS(544,514) as defined in IEEE 802.3 using codeword interleaving.
• The RS-FEC supports external statistics collection by providing a statistics vector which provides information for codewords, corrected codewords, uncorrected codewords as well as individual symbols corrected per codeword if corrections occurred. Option to integrate RS-FEC Statistics module.
• Pseudo-random test-pattern generator and checker for transmiter and receiver testing.
• Fault detection capable of indicating faults that render a link unreliable (loss of synchronization or excessive bit errors).
• Generic host interface allowing direct access to all configuration and status registers.
• Multi-channel support with support for 4 * 400G (802.3 Clause 119) and 2 * 800G (Draft 802.3df) and 1.6T (Draft 802.3dj)
• Optional single channel 1.6T PCS.

Benefits

• Supports all required features of the IEEE 802.3 specification and draft specifications
• IP available in single 1.6T mode and quad channel mode supporting 4 x 400G,
• 2 x 800G and 1.6T
• Designed to be used with Synopsys 1.6T MAC IP for 1.6T Ethernet Systems
• Includes RS-FEC functions
• Integration tested with the 1.6T Ethernet MAC and 224G Ethernet PHY IP

Applications

• High-speed interconnect for AI / Machine Learning processing
• High-Performance Networking
• High-Performance Computing

Deliverables

• SystemVerilog RTL Source code
• Verilog Testbench environment with example testcases
• Scripts and constraints files for implementation tools like Spyglass Lint/CDC, DesignCompiler, etc.
• IPXACT views for register maps

Technical Specifications