Super-Fast 8051 Microcontroller Core with Configurable Features and Peripherals

Overview

The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set and includes a configurable range of features and integrated peripherals.

The core’s sophisticated architecture yields the fastest 8051-compatible 8-bit MCU available anywhere (at the time of its release). It runs with a single clock per machine cycle, and requires an average of 1.5 to 1.8 machine cycles per instruction, depending on configuration. Dhrystone 2.1 tests show it to run from 9.41 to 26.85 times faster than the original 8051 at the same frequency, without requiring an external arithmetic acceleration unit (such as an MDU). Representative 65nm LP ASIC results have reached 500 MHz, for an effective speed-up of 1,000 times over 80C51 chips. Interrupt latency is a remarkably low two cycles.

The S8051XC3 is also one of the most energy efficient 8-bit processors available. Its small silicon footprint—the CPU size can be under 6,500 gates—means very little power leakage. Furthermore, dynamic power of the CPU at a 40nm technology is as low as 2.3μW/MHz, and its higher performance allows clocking at lower frequencies. The core allows energy consumption to be adjusted to the processing workload via dynamic frequency scaling and independent control of the CPU and peripherals clock.

The core’s rich set of optional features and integrated peripherals allows designers to adjust performance and silicon requirements to best match an application’s specific requirements. (Several pre-configured versions at different price points are also available.) Software development is facilitated by a single-wire or JTAG debugging interface, which operates seamlessly within IDEs such as those from IAR and Keil.
This new core builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous or asynchronous reset, and no internal tri-states.

Key Features

Fully compatible with the MCS®51 instruction set
Best Performance Available

Up to 26.85x speed-up over the original 8051 at the same clock
More than 1,000 times faster than the original 8051 when clocked at maximum frequency

Energy Efficient

Small silicon footprint for less power leakage, lower static power consumption
Better DMIPs/MHz power ratio allows energy to be saved by operating at a lower frequency
Ultra-low dynamic power (2.3μW/MHz in 40nm)
Advanced power management supports dynamic frequency scaling, and CPU and/or peripherals clock gating

Configurable Microcontroller

Automatic instantiation of user selectable MCU peripherals
Pre-integration with other CAST IP on request
User-configurable CPU and memory architecture to match application needs

Easy Firmware Development

CDP-XC on-chip debug interface, supports JTAG and Single-Wire
USB-based, low cost CDP-XC debug pods

Integration with IAR Embedded Workbench & Keil uVision™ IDEs

Software and Hardware breakpoints, and Trace
Cycle-accurate Simulation Model

Flexible Memory Architecture

64KB or 8MB address space
8, 16, or 32-bit memory interface
Integration with slow memories or peripherals easier with acknowledged transactions
Independent XTEM bus
Optional extra 16-bit or 24-bit DPTR

Efficient Interrupts Handling

Up to 23 interrupts, with 2 or 4 interrupt priority levels
Ultra-low interrupt latency: two cycles from interrupt assertion to ISR start

Block Diagram

Applications

The royalty-free S8051XC3 is a resource- and cost-effective solution for offloading main processors in complex SoCs, running deeply embedded systems, or managing analog sensors and other peripherals in IP subsystems. Application areas include Internet of Things (IoT) and wearable electronic devices, industrial control systems, and more.

Deliverables

The core is available in Verilog RTL or as targeted FPGA netlist, and its deliverables include everything required for a successful implementation, including a behavioral model, an automated constrained random verification (CRV) test-bench, comprehensive documentation, and sample synthesis and simulation scripts. Hardware debug pods and reference design boards are also available.

Technical Specifications

Maturity

Production Proven

Availability

Now

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