CoreRSDEC is an RTL generator that produces an Microsemi FPGA–optimized Reed-Solomon (RS) decoder core based on user-defined parameters. RS codes are a class of error-correcting codes used to detect and correct errors that might be introduced into digital data when it is transmitted or stored. Error-correcting codes incorporate redundancy in data. With this redundancy, only a subset of all possible transmissions contains valid messages. This means the valid codes are separated from each other so errors are not likely to corrupt one valid code into another. The encoded data can then be transmitted or stored.
Key Features:
* Flexible RS Decoder meeting the requirements of most standards that employ RS codes
* Supports continuous output data with no gap between code blocks
* Supports a code block length variable up to 255 symbols
* Supports a symbol width from 3 to 8 bits and supports any primitive field polynomial for a given symbol width
* Supports shortened codes