Programmable Mode AES Encrypt/Decrypt Core

Overview

The AES-P encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.

Two architectural versions are available to suit system requirements. The Standard version (AES-P-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-P-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cypher modes: ECB, CBC, OFB, CFB and CTR.

The core works with a pre-expanded key, or with optional key expansion logic.

The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.

Key Features

Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
Implemented according to the Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
NIST Certified
Processes 128-bit data in 32-bit blocks
Employs user-programmable key size of 128, 192 or 256 bits
Two architectural versions:
Standard is more compact:
32-bit data path size
Processes each 128-bit data block in 44/52/60 clock cycles for 128/192/256-bit cipher keys, respectively
Fast yields higher transmission rates:
128-bit data path
Processes each 128-bit block in 11/13/15 clock cycles for 128/192/256-bit cipher keys, respectively
Supports Electronic Codebook (ECB), Cipher Block Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB) and Counter (CTR) modes
Works with a pre-expended key or can integrate the optional key expansion function
Simple, fully synchronous, reusable design
Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
Complete deliverables include test benches, C model and test vector generator

Block Diagram

Applications

Protected network routers
Electronic financial transactions
Secure wireless communications
Secure video surveillance systems
Encrypted data storage

Deliverables

HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Sophisticated HDL Testbench (self checking)
C Model & test vector generator
Simulation script, vectors & expected results
Synthesis script
User documentation

Technical Specifications

Maturity

Production Proven

Availability

Now

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