The power-on-reset(POR) generates a reset pulse to ensure that the core processing circuits are in a defined state when the power is ramping up or ramping down. The POR detects the safe supply thresholds and protects the core circuits in case of supply regulation problems.
The inbuilt timer in POR generates a delays in the power-up to keep the chip in desired configuration. Once the supply is in safe limits and defined delay is provided, the POR generates a negative pulse to reset the core circuits. Thus, when reset is released the core is always in a defined state.
POWER ON RESET FOR 3.3V SUPPLY
Overview
Key Features
- Input voltage from 2.7V to 3.6V
- -40°C to +125°C Operating Temperature Range
- Low power POR with typical 2.5µA Operating Consumption
- 20µs typical delay for proper reset
Applications
- Battery-powered applications
- Smartphones, Tablets and wireless LAN devices
- Industrial and medical equipments
Deliverables
- Dataseet
- Behavioral model
- Abstract LEF
- Timing LIB files
- CDL
- GDSII
- Full integration support
Technical Specifications
Foundry, Node
180nm
Maturity
Silicon matured