PDM Verification IP

Overview

PDM can digitally represents high quality audio, and is inexpensive and easy to implement. In PDM,an analog signal can be directly sampled at a high sampling rate and converted to a PDM stream.

PDM Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

PDM Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Full PDM Transmitter and Receiver functionality
Supports 8,10,12,16,20,24,32 bit data precision
Supports PDM modulator and PDM demodulator
Supports PDM Digital output
Supports PDM error output
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Status counters for various events on bus.
Callbacks in transmitter, receiver and monitor for various events.
Supports constraints Randomization.
Built in functional coverage analysis.
PDM Verification IP comes with complete test suite to test every feature of PDM specification.

Benefits

Faster testbench development and more complete verification of PDM designs.
Easy to use command interface simplifies testbench control and configuration of master and slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the PDM testcases.
Examples showing how to connect various components, and usage of Master, Slave and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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