OCTAL SPI Master IP

Overview

Key Features

• Full Octal SPI Master Functionality
• Fast frequency support(Up to 133MHz)
• Compliant to the SPI de-facto standard
• Single, dual, quad and octal serial data lines
• Software programmable transmission formats (CPOL and CPHA)
• Up to 16 slaves supported under master control
• Configurable SPI transfers
• Fast sampling clock input for the SPI transfers
• Copyright +® SmartDV IP Solutions Private Limited
• SPI Block Specs compliant
• FIFOs used for transferring data (configurable depth)
• Full duplex operation
• LSB or MSB mode
• 8-bit, 16-bit, 24-bit and 32-bit synchronous serial transmission
• Software programmable SCLK rate
• Supports DMA/HCI (Host controller Interface) mode of operation.
• Interrupt control
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Deliverables

• The OCTAL SPI MASTER interface is available in Source and netlist products.
• The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and linux driver package
• Documentation contains User s Guide and Release notes.

Technical Specifications