Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of communication protocols defined by MIPI Alliance standards intended for mobile system chip to chip communications. The CSI-2 specification is specially targets for Camera to Image application processor communication.
Innosilicon CSI-2 Receiver operates as a receiver of a CSI-2 link, which consists of an Innosilicon D-PHY and an Innosilicon CSI-2 controller.
? The D-PHY is used for the data transmission from a CSI-2 compliant camera sensor. In D-PHY, the link includes a High-Speed signaling for fast-data traffic and a low-power signaling mode for control purposes. Error information is generated for application layer to do further operation.
? The CSI-2 Receiver Controller works as a protocol layer between application layer and physical layer. It implements all three layers defined by CSI-2 Specifications, including Pixel Unpacking, Low Level Protocol, and Lane Management.
MIPI D-PHY CSI-2 RX IP
Overview
Key Features
- Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) V1.3
- Compliant with MIPI Alliance Standard for D-PHY Specifications V1.2
- 2.5Gbps maximum data transfer rate per lane (D-PHY)
- Implements all four CSI-2 MIPI Layers (PHY Layer, Lane Management Layer, Low Level Protocol and Byte to Pixel Unpacking Formats)
- Asynchronous transfer at low power mode with a bit rate of 10Mbps on D-PHY supported
- Unidirectional mode supported
- Support lane de-skew
- Support date type: RGB/YUV/RAW (Based on actual application scenarios)
- Error detection and correction supported
- Automatic termination control
Deliverables
- Databook and detailed physical implementation guides for the complete PHY
- Library Exchange Format (LEF) file with pin size and locations
- Gate-level netlist and Standard Delay Format (SDF) Timing file
- Layout Versus Schematic (LVS) flattened netlist in spice format and report
- Encrypted Verilog Models
- GDSII database for foundry merge
- Module integration guidelines
- Silicon validation report (when available)
- Evaluation board (when available)
Technical Specifications
Foundry, Node
SMIC 40/14nm
SMIC
In Production:
14nm
,
40nm
LL
Related IPs
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables
- MIPI D-PHY Rx ONLY v1.1 @1.5ghz Ultra Low Power & Low Area for IoT & Wearables
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+