With sophisticated architecture and advanced technology, JESD204B X8 RX IP with PHY only is designed for low power and high-performance application. It is fully compatible with JESD204B specification, and supports link rate from 1.6875Gbps to 16Gbps.
The IP is designed for JESD204B RX, which de-assembles the parallel data from the 204b links into SOC or DACs.
JESD204B RX IP
Overview
Key Features
- X8 Lane Mode, up to 16Gbps per lane
- Serialization interface width
- PHY- User interface support 16/20/32/40 bit
- Shared common PLL based architecture
- Digitally-control-impedance termination resistors and On-chip resistance calibration
- Rx Built-in Decision Feedback Equalization (4 Taps)
- 2nd order Wide Range Phase-Interpolator Based Digital CDR
- PLL Frequency Lock detection
- Support BIST, and Analog DC Testing
- Support Flip-chip package
Benefits
- X8 Lane Mode, up to 16Gbps/lane
- Fully Compatible with the JESD204B standard release
- Supports Subclasses 0, 1
- Serial lane alignment and monitoring
Applications
- High Speed ADC/DAC
- 5G RF Transceiver
- Base Station
Deliverables
- GDSII&CDL Netlist
- Verilog Model
- LEF Layout Abstract(.LEF)
- Liberty Timing Models(.lib)
- Verify Results
- Specification
- Datasheet
- Integration Guideline
- Evaluation Plan
- Leading support for package design, SI&PI modeling and production test development
Technical Specifications
Foundry, Node
28nm
Maturity
Silicon Proven