High Bandwidth Low Jitter De-Skew PLL

Overview

High bandwidth de-skew PLL for minimizing clock tree timing uncertainty. Low Power/ Low Area hard macro with industry leading jitter performance for its power/area class.

Key Features

Wide input and output frequency ranges
Duty cycle 48% -- 52%
Static Phase Offset 1% UI
Multiple synchronous output clocks
Small footprint (0.003mm2 to 0.04mm^2)
Low power
Low jitter:
Core supply voltage only
Built-in supply decoupling
Simple digital control interface

Benefits

4:1 VCO range allows any frequency below the maximum VCO rate to be de-skewed
High bandwidth PLL quickly adjusts to track input phase variations
No external components required
No additional supply decoupling required
Loop automatically adjusts for any input frequency, so no complicated programming is required

Deliverables

GDSII
CDL Netlist (MG Calibre Compatible)
Functional Verilog Model
Liberty timing models (.lib)
LEF
Application Note

Technical Specifications

Foundry, Node

TSMC, Global Foundries, Samsung, SMIC, UMC - 3nm - 180nm

Maturity

Silicon Proven

Availability

Available Now

GLOBALFOUNDRIES

In Production: 28nm HPP , 28nm SLP , 55nm
Pre-Silicon: 14nm LPP , 40nm LP , 55nm LPX , 65nm , 65nm LP
Silicon Proven: 65nm LPe

Intel Foundry

Pre-Silicon: 16nm

SMIC

In Production: 28nm HK , 40nm LL
Pre-Silicon: 55nm G , 55nm LL , 65nm LL
Silicon Proven: 28nm PS

Samsung

Pre-Silicon: 8nm , 10nm

TSMC

In Production: 5nm , 7nm , 10nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP , 65nm GP
Pre-Silicon: 28nm LP , 45nm GS , 45nm LP , 55nm GP , 55nm LP , 65nm G , 65nm LP , 80nm , 80nm GT , 80nm HS , 90nm G , 90nm GOD , 90nm GT , 110nm G , 110nm LVP , 130nm , 130nm G , 130nm LP , 130nm LV , 130nm LVOD
Silicon Proven: 3nm , 4nm , 6nm , 28nm HP , 90nm LP

UMC

In Production: 28nm HPC , 55nm
Pre-Silicon: 28nm HLP , 28nm HPM , 65nm SP

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