Frac-N SSCG PLL - TSMC 6FF

Analog Bits’ low power Fractional-N / SSCG PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, clock tracking or fine tuning on-the-fly, and Spread Spectrum clock generation. The PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces