Chiplet Solution

Overview

Based on the traditional advantages of SerDes and DDR IP, KNiulink Semiconductor has launched a solution that meets the UCIe standard based on local requirements of domestic chip customers. The D2D products designed and implemented by the team in the early stage successfully realized the chip interconnect based on localization and low cost. At present, high transmission rate and bandwidth products based on advanced technology have been formed, with multiple series of mature PHY and MAC structures, supporting heterogeneous integration of multi-process nodes. The KNiulink D2D products provide excellent PPA performance.

Key Features

Low cost design support for domestic package
Compatible with UCIe standard&advanced package, provide PHY + MAC-Package-Testability solution with domestic PET manufacturer
Provides full SIPI channel physical layer simulation analysis
Supports advanced packaging (Interposer) and standard packaging channel simulation verification, to meet the high bandwidth, high data volume application requirements
Optimized design with SerDes and DDR technology
Combines SerDes and DDR technology to optimize the design in different directions, such as latency, power consumption, area and high bandwidth, to meet the characteristics of various applications
Supports die-to-die Adapter interconnect layer in UCIe, Physical Layer specification

Benefits

Low cost design
latency, power consumption, area and high bandwidth, to meet the characteristics of various applications
die-to-die Adapter interconnect layer in UCIe

Applications

High Performance Computing Storage
MPU
GPU
FPGA System

Deliverables

GDSII&CDL Netlist
Verilog Model
LEF Layout Abstract(.LEF)
Liberty Timing Models(.lib)
Verify Results
Specification
Datasheet
Integration Guideline
Evaluation Plan
Leading support for package design, SI&PI modeling and production test development

Technical Specifications

Foundry, Node

180/12nm

Availability

Available

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