Baseline JPEG Encoder with optional Constant Bitrate Motion JPEG Video Rate Control

Overview

The JPEG-E core from Alma Technologies is a standalone and high-performance JPEG encoder for still image and video compression applications. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 standard makes the JPEG-E core ideal for interoperable systems and devices.

In addition to generating standalone Baseline JPEG streams, the core can also produce the (de-facto) standard video payload of many motion JPEG container formats. Furthermore, the bandwidth constrained applications can benefit from the optionally included constant bitrate video rate control block.

The core is designed with simple, fully flow-controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG-E is a reliable and easy-to-use and integrate IP.

Key Features

  • Complete, Compliant and Standalone Operation
    • 8-bit Baseline JPEG encoder with full ISO/IEC 10918-1 compliance
    • Up to 64K x 64K image resolution
    • 1-4 image components
    • 1, 2 and 4 horizontal and vertical sampling factors support
    • Single- and multi-scan support
    • Programmable Quantization Tables (up to four)
    • Programmable Huffman Tables (two DC, two AC)
    • Programmable Restart Markers insertion
    • Complete and standalone Baseline JPEG stream output with user controllable marker inclusion
    • CPU-less operation
    • Single clock cycle per sample encoding throughput
  • Extra Capabilities
    • Programmable Quality Factor (1 to 100) for easy Quantization Tables scaling
    • Motion JPEG payload encoding
    • Optional block-based maximum output size control with independent Luminance and Chrominance bit thresholds
    • Optional high-quality and accurate video rate control
      • Automatic Quality Factor adjustment per frame
      • Programmable nominal compressed frame size
      • Programmable bandwidth shaping output buffer size
    • Ease of Integration
      • Simple, microcontroller like, programming interface
      • High-speed, flow controllable, streaming I/O data interfaces
        • Simple and FIFO like
        • Avalon-ST compliant (ready latency 0)
        • AXI4-Stream compliant
      • Trouble-Free Technology Map and Implementation
        • Fully portable, self-contained RTL source code
        • Strictly positive edge triggered design
        • D-type only Flip-Flops
        • Fully synchronous operation
        • No special timing constraints required
          • No false paths
          • No multi-cycle paths

        Block Diagram

        Baseline JPEG Encoder with optional Constant Bitrate Motion JPEG Video Rate Control Block Diagram

        Deliverables

        • Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized & verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
        • Release Notes, Design Specification and Integration Manual documents
        • Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
        • Self checking testbench environment, including sample BAM generated test cases
        • Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

        Technical Specifications

        Maturity
        Silicon Proven
        Availability
        NOW
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Semiconductor IP