Baseline JPEG Codec with optional Constant Bitrate Motion JPEG Video Rate Control

Overview

The JPEG-C core from Alma Technologies is a standalone and high-performance, half-duplex Baseline JPEG codec for still image and video compression applications. Full compliance with the Baseline Sequential DCT mode of the ISO/IEC 10918-1 JPEG standard makes the JPEG-C core ideal for interoperable systems and devices.

In addition to the standard Baseline JPEG streams, the core is also capable of supporting the video payload of many (de facto) standard motion JPEG container formats. The JPEG-C can also be enhanced with an optional add-on bit-rate control block, which will benefit the bandwidth constrained applications.

The core is designed with simple, fully controllable and FIFO-like, streaming input and output interfaces. Being carefully designed, rigorously verified and silicon-proven, the JPEG-C is a reliable and easy-to-use and integrate IP.

Key Features

Baseline ISO/IEC 10918-1 JPEG Compliance.

Programmable Huffman Tables (two DC, two AC).
Programmable Quantization Tables (up to four).
Up to four color components.
Supports all possible scan configurations and all JPEG formats for input and output data.
Supports any image size up to 64K x 64K.
Supports DNL and restart markers.

Additional Processing Capabilities:

Motion JPEG payload support.
Rate-Control (optional).

Limitations with Respect to the ISO/IEC 10918-1 JPEG Standard:

Up to 4 image components are supported.
Supported sampling factors: 1, 2 and 4.
Decoding of corrupted JPEG streams is not supported.

Ease of Integration.

Simple, microcontroller like, programming interface.
High speed, flow controllable, streaming I/O data interfaces.

Simple and FIFO like.
Avalon-ST compliant (ready latency 0).
AXI4-Stream compliant.

Decoding:

Stand alone operation.
Automatic self-programming by JPEG markers parsing.
Marker errors catching.

Encoding:

Single clock per input sample processing rate.
Automatic JPEG markers generation on the output.

Trouble-Free Technology Map and Implementation.

Fully portable HDL source code.
No internal tri-states.
Strictly positive edge triggered design using D-type only Flip-Flops.
Fully synchronous operation.
No need for special timing constraints.

No false paths
No multi-cycle paths

Block Diagram

Deliverables

Clear text VHDL or Verilog RTL source for ASIC designs, or pre-synthesized & verified Netlist for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices
Release Notes, Design Specification and Integration Manual documents
Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
Self checking testbench environment, including sample BAM generated test cases
Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts

Technical Specifications

Maturity

Silicon Proven

Availability

NOW

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