AMBA AHB Device/Host Bridge

Overview

This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices.

The bridge supports Host Mode and Device Mode (selected by a dedicated input pin). In Host Mode, the bridge is in charge of PCI bus arbitration and generating the PCI reset signal. In Device Mode, the bridge implements a PCI target enabling PCI access to the AMBA AHB bus space behind the bridge.

The bridge enables higher utilization of the bus’ available bandwidth by prefetching PCI data and buffering AHB data, and allows the host to initiate PCI accesses or to respond to transactions initiated by other PCI devices.

The core complies with the PCI bus specification versions 3.0 and 2.3, and can act as a PCI master and target. Furthermore if implements PCI bus arbitration, supporting up to seven PCI bus agents, PCI reset signal generation, and all types of PCI transactions provisioned by the standard.
The host connects to the bridge via master and a slave 32-bit AMBA/AHB bus interfaces. The AHB slave interface allows the host to access the status and to control registers and initiate PCI Transfers, while data from the PCI target is communicated to the host via the AHB master interface.

The PCI-DHB-AHB builds on more than 10 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.

Key Features

PCI Device/Host Bridge

Pin-selectable PCI Host Bridge or PCI Device operation
Enables data communication between the Host Processor residing on an AHB bus and devices on the PCI bus
PCI I/O space and memory space are mapped directly to the AMBA AHB memory space
PCI Interrupt and System Errors are propagated as interrupts to the host
PCI Configuration registers are accessible from both PCI and host directions
Advanced PCI data prefetching and AHB data buffering for improved bus bandwidth utilization
Asynchronous AMBA/AHB and PCI clocks

PCI Interface

PCI specification 3.0 and 2.3 compliant

33/66 MHz
32-bit bus width
32-bit address space
Parity generation and parity error detection

PCI Master & Target and Device support all types of transactions:

Configuration space read/write
Memory space read/write
I/O Space read/write
Interrupt acknowledge (optional)
Special cycles (optional)

PCI reset generator
PCI bus arbiter

Up to 7 external bus agents
Flexible priority schemes
Agent malfunction detection and reporting

AHB Interface

32-bit AMBA/AHB v2.0 host interface
AHB Slave enables host to initiated PCI transaction and access configuration registers
AHB Master delivers data from the PCI target interface to the host

Block Diagram

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Sophisticated HDL Testbench
Simulation script, vectors, expected results, and comparison utility
Synthesis script (ASICs) or place and route script (FPGAs)
Comprehensive user documentation, including detailed specifications and a system integration guide

Technical Specifications

Maturity

Production Proven

Availability

Now

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