The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Designed for fast integration, low gate count, and maximum performance, the AES Engines provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs.
AES-ECB-CBC-CFB-OFB-CTR Crypto Accelerator
Overview
Key Features
- Wide bus interface.
- Key sizes: 128, 192 and 256 bits.
- Key scheduling hardware.
- Feedback modes: ECB, CBC, CTR, OFB (128 bit), CFB (1-, 8- and 128-bit).
- Fully synchronous design.
- Low Speed, Medium Speed, High Speed versions.
- Encrypt-only versions (aimed at Counter Mode) for each speed version.
- Fully synchronous design
Benefits
- High-speed AES solution
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
- Complete range of configurations
- World-class technical support
Deliverables
- Documentation
- Hardware Reference and Programmer Manual
- Integration Manual
- Verification Specification
- Synthesizable Verilog RTL source code
- Self-checking RTL test bench, including test vectors and expected result vectors
- Simulation scripts
- Configurations:
- EIP-36b
- High-speed Encrypt/Decrypt
- 52k gates
- 12.8 bits/clk
- up to 1 GHz
- EIP-36c
- High-speed Encrypt only
- 35K gates
- 12.8 bits/clk
- up to 1 GHz
- EIP-36d
- Medium-speed Encrypt/Decrypt
- 34k gates
- 4.0 bits/clk
- up to 1 GHz
- EIP-36e
- Medium-speed Encrypt only
- 37k gates
- 4.0 bits/clk
- up to 1 GHz
- EIP-36f
- Low-speed Encrypt/Decrypt
- 28k gates
- 2.46 bits/clk
- up to 1 GHz
- EIP-36g
- Low-speed Encrypt only
- 23k gates
- 2.46 bits/clk
- up to 1 GHz
Technical Specifications
Foundry, Node
Any
Maturity
Silicon Proven
Availability
Now
TSMC
Silicon Proven:
7nm
,
16nm
,
28nm
,
40nm
G