ZUC Crypto Accelerator

Overview

Key Features

• ZUC 3GPP compliance
• ETSI/SAGE v1.6 compliant:
• ZUC key stream generator [ZUC]
• 128-EEA3 Confidentiality mode [EEA3-EIA3]
• 128-EIA3 Integrity mode [EEA3-EIA3]
• Engine aspects
• Fully synchronous design
• Pipelined high-speed Wide-bus interface
• 128-bit cipher key
• 128-bit IV
• Supported modes
• Basic encryption/decryption
• Key stream generation
• 128-EEA3 Confidentiality mode
• 128-EIA3 Integrity mode
• WIDE-BUS INTERFACE
• Data input - 32-bit wide
• Data output - 32-bit wide
• Key input - 128-bit wide
• IV input - 128-bit wide
• Length input - 16-bit wide
• Mode input - 3-bit wide
• VERIFICATION
• Python and Verilog based self-checking verification environment.
• Delivered with a test vector set for chip integration verification.
• Integration test vectors in structured format.
• 100% verification coverage.

Benefits

• High-speed ZUC solution
• Silicon-proven implementation
• Fast and easy to integrate into SoCs
• Flexible layered design
• Complete range of configurations
• World-class technical support

Applications

• 3GPP Wireless communication
• 4G mobile communications
• Femtocell handsets and base stations
• eNodeB base stations

Deliverables

• Documentation
• Hardware Reference and Programmer Manual
• Integration Manual
• Verification Specification
• Synthesizable Verilog RTL source code
• Self-checking RTL test bench, including test vectors and expected result vectors
• Simulation scripts
• Configurations:
• EIP-48b
• High-speed
• 24K gates
• 32.0 bits/clk
• up to 800 Mhz
• EIP-48c
• High-frequency
• 25k gates
• 16.0 bits/clk
• up to 1.1 Ghz
• EIP-48d
• Medium-speed
• 20k gates
• 8.0 bits/clk
• up to 1 GHz

Technical Specifications