64G SerDes

Overview

The KNiulink 64G SerDes IP core supports PAM4 signaling in the range of 25.0 - 64.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero (NRZ) signaling is supported in the range of 2.5 - 32.0 Gbps using full, half, and quarter-rate modes. Either scrambled or block coded (for example, 8B/10B) data is supported for 2.5 - 12.5 Gbps in NRZ mode. However, scrambled data is required for data rates greater than 12.5 Gbps.
The 64G SerDes IP cores are intended for use as a chip-to-chip or a card-to-card connection mechanism.

Key Features

  • 4 Channels per Quad, <=64Gbps;
    • PAM4 support 25~64Gbps;
    • NRZ support 2.5~32Gbps;
  • Serialization/Deserialization interface width;
    • 64/32/16bits;
    • 64-bit parallel data path in PAM4 mode;
    • 32-bit parallel data path in full-rate NRZ mode;
    • 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes;
  • Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines;
  • Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades;
  • Feed Forward Equalization (FFE) driver equalization;
  • Adaptive and configurable RX Continuous Time Linear Equalizer (CTLE), Feed Forward Equalizer (FFE) and Decision Feedback Equalizer (DFE);
  • Digital-based receiver consisting of the following:
    • Analog Front-End (AFE)
    • Analog-to-Digital Converter (ADC)
    • Digital Signal Processor (DSP)
  • Digitally-control-impedance termination resistors;
  • Configurable Tx output differential voltage swing;

Benefits

  • Support for manufacturing and system test;
  • Generalized scan design compliant with manufacturing functional (macro) tests;
  • Full-rate loopback and Built-In Self-Tests (BIST) with selectable PRBS patterns;
  • Compatible with IEEE 1149.6-2003 ACJTAG;
  • Supports Flip-Chip package

Applications

  • 400/800G Communication
  • Hyperscale Data Center
  • AI and Machine Learning

Deliverables

  • GDSII&CDL Netlist
  • Verilog Model
  • LEF Layout Abstract(.LEF)
  • Liberty Timing Models(.lib)
  • Verify Results
  • Specification
  • Datasheet
  • Integration Guideline
  • Evaluation Plan
  • Leading support for package design, SI&PI modeling and production test development

Technical Specifications

Foundry, Node
12nm
Maturity
Developing
×
Semiconductor IP