32-bit/33,66Mhz PCI Host Bridge

Key Features

• PCI specification 2.2 compliant
• 33/66 MHz performance
• 32-bit datapath
• PCI reset generator
• PCI bus arbiter (up to 7 external bus agents)
• Interrupt controller
• Parity generation and parity error detection.
• Dual-port based shared memory
• PCI Configuration registers accessible from both PCI and host directions

Benefits

• Enables data transfers between a host processor system and PCI bus based devices.
• Bridge is in charge of PCI bus arbitration, generating PCI clock and reset signals.
• An important part of the bridge is the bus arbiter.
• Is a generic core, which provides all the essential bridge functions without a host bus interface.

Deliverables

• VHDL RTL source code for PCI-HB
• VHDL RTL source code for DMA Controller
• Testbench
• Vectors for testbench
• Expected results for testbench
• Simulation and synthesis scripts
• Documentation

Technical Specifications