3.3V - >1.2V/1.1V/0.9V Low Power Cap-less LDO IP Core
Overview
A 3.3V - >1.2V/1.1V/0.9V Low Power Cap-less LDO (Low Drop-Out) is a type of voltage regulator designed to provide a stable output voltage of 0.9 volts from a 3.3-volt input voltage source. It is typically used in low-power applications where a low output voltage is required for digital circuits or other components.
Key Features
- Low Dropout Voltage
- Low Output Voltage
- Low Quiescent Current
- Low Noise
- Thermal Shutdown Protection
- Reverse Current Protection
- Short-Circuit Protection
- Overload Protection
- Wide Operating Temperature Range
- Low Power Consumption
Deliverables
- GDS
- LVS Spice netlist
- Verilog mo
- User Guidelines including: integration guidelines, layout guidelines, testability guidelines, packaging guidelines, board-level guidelines
Technical Specifications
Maturity
In Production
Availability
Immediate
Related IPs
- Low Power 5V->3.0V Cap-less LDO IP Core
- I2C Controller IP – Slave, SCL Clock only, principally for configuring registers in mixed-signal ICs with low noise or low power requirements
- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
- DPA- and FIA-resistant Ultra Low Power FortiCrypt AES IP core
- 3.3V ->1.1V/0.9V Cap-less LDO IP Core
- Low Power 5V->2.4V Low noise LDO IP core