16G UCIe Standard PHY for TSMC 7nm

Overview

UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

The Cadence® UCIe IP complete solution meets the growing demand for high performance and bandwidth, superior power efficiency, and ultra-low latency interconnect between dies on different foundries and process nodes. The Cadence® 16G UCIe PHY provides an industry chiplet interoperable solution for on-die integration, as it caters to growing system-in-package (SiP) applications. Standard and advanced UCIe PHY options offer flexibility for designers in implementing a wide range of packaging options. The UCIe PHY IP employs Known Good Die (KGD) techniques and is engineered to quickly and easily integrate into any system-in-package (SiP). It is verified with the UCIe Controller IP as part of a complete UCIe subsystem solution, which also includes Cadence UCIe Verification IP (VIP). The Cadence UCIe total solution offers ease of integration of both the PHY and controller IP in an open chiplet ecosystem.

Key Features

  • 16Gbps per pin and supports 12/8/4Gbps subrates
  • High bandwidth, ultra-low latency, superior power efficiency, and low-power modes
  • BIST features ensure Known Good Die (KGD)
  • Sideband for link management and robust training
  • Interoperable between different technology nodes and foundries on the UCIe chiplet ecosystem
  • Flexible pitch enables maximum bandwidth throughput
  • Width degradation capability in standard package PHY
  • Background calibration during mission mode
  • Comprehensive characterization and test hooks
  • Supports laminate or organic substrate packages for cost-effective performance

Applications

  • High Performance Compute,
  • AI,
  • ML,
  • Servers,
  • Networking,
  • Communications,
  • Consumer Electronics,
  • Data Processing,
  • Industrial and Medical,
  • Military/Civil Aerospace

Deliverables

  • Integration views: LEF abstract, timing views (.LIB), Verilog behavioral model, gate-level netlist, SDF, DRC, LVS, ANT reports, and GDSII layout and layer map
  • Verilog testbench with example run scripts, demonstration tests, and bus functional models
  • Full documentation set including integration, user, and programmer guides
  • DFT collateral including ATPG generation and setup guidelines and scan abstracts (CTL), High Volume Manufacturing (HVM) kit
  • IPXACT register abstracts, IBIS-AMI kit

Technical Specifications

Foundry, Node
TSMC 6nm, 7nm
Maturity
Available on request
TSMC
Pre-Silicon: 6nm , 7nm
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Semiconductor IP