2D / 3D IP

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Compare 32 2D / 3D IP from 7 vendors (1 - 10)

2D Graphics Hardware Accelerator (AXI4 Bus)
- Bit Block Transfer - 3 Independent Memory Sources of data
- .2D Raster Operations (ROP) performed on Block Transfers
BitBLT Graphics Hardware Accelerator (AHB Bus)
- Bit Block Transfer – 3 Independent Memory Sources of data:
- 2D Raster Operations (ROP) performed on Block Transfers:
- BitBLT Draw Features:
- 2D Graphics Rendering Engine (Option):
JVC Object-Based Gloss Enhancer
- New type contrast and sharpness enhancer which creates vivid and glossy 3-D feeling images based on objects
- Improve contrast feeling without handling gamma by applying human optical sensory property
- No external memory required. Easy to implement
BitBLT Graphics Hardware Accelerator (AXI4 Bus)
- Bit Block Transfer – 3 Independent Memory Sources of data:
- 2D Raster Operations (ROP) performed on Block Transfers:
- BitBLT Draw Features:
- 2D Graphics Rendering Engine (Option):
ISP, Image Signal Processing, Real-time Pixel Processor for Automotive
- Very low latency
- no frame-buffer
Image Signal Procesing, Real-time Pixel Processor Automotive
- Very low latency
- no frame-buffer
Advanced 2D Graphics Contoller
- Fully synchronous, synthesizable and technology independent RTL code
- Capable of drawing shapes such as pixels, lines and rectangles
JPEG 2000 HD 60P Decoder
- Up to 1 HD 60p channel or 2 HD 30p / 50i / 59,9i / 60i channels
- Visually lossless compression
- Xilinx 7 Series FPGA (Zynq-7, Artix-7, Kintex-7, Virtex-7), Xilinx Virtex-6 & Spartan-6
- Altera Cyclone V, Arria II & V, Stratix IV and V
Image Signal Processor IP
- Support 8-16 Bit Bayer RAW and ITU-R BT.601 & 656 Video Interface
- Test Pattern Generator(TPG)
- Black Level Measurement and Compensation (BLS)
- Sensor linear correction
Image Signal Processor IP
- Support maximum resolution: 8K
- Support DVP Input Interface
- Support 32 Bit Bayer RAW Video Interface and 8-10 Bit ITU-R BT.601 & 656 Video Interface
- Test Pattern Generator (TPG)