Cadence Low-power Verification: Tear Down These Walls

By Cadence

November 4, 2010

You've been building chips for years and the growing complexity means you just can't tolerate simple tool-to-tool flows and group-to-group barriers any more. SystemC and RTL in the same low-power simulation?  Got it.  Mixed-signal?  Yep.  Every team with fingers in the power intent?  For sure.  Siicon Realization is real to you because you're living it, but you need more from EDA so you're demanding "Cadence Low-power Verification: Tear Down These Walls!!"

So why is the product manager for the Incisive Enterprise Simulator, a seemingly siloed product, blogging about this?  Because it's my life too.  If you've invited me to your site in the past year, you know my roadmap presentation has 150+ slides.  It's not becuase I'm running each team through every button and switch in our simulator.  It's because the simulator itself has blown through the barriers.  Sure, we cover traditional topics like SystemVerilog, coverage, and assertions.  But we also talk about low-power, mixed-signal, and project-level performance.  We have to because you live this integration.

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