NAND Flash PHY IP
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18
NAND Flash PHY IP
from 4 vendors
(1
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10)
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ONFI 5.0 PHY
- The PHY design supports the newly introduced NV-LPDDR4 mode along with SDR, NV_DDR, and NV_DDR2, NV_DDR3 mode.
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
- Programmable timing
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ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
- Page Size – 2KB, 4KB, 8KB, 16KB
- Bank/chip select options
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ONFI 4.0 NAND Flash Controller & PHY
- • Support ONFI 4.0, EZ – NAND, Standard ClearNAND, Advanced ClearNAND
- • Support standard asynchronous NAND flash
- • High performance from 40MT/s to 800MT/s
- • High density NAND flash up to 1024 Gb
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NAND Flash Synthesizable Transactor
- Supports 100% of NAND Flash protocol standard of HY27UH08AG(5/D)M
- Supports all the NAND Flash commands as per the specs
- Supports NAND interface of x8 width
- Supports multiplexed address/data
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ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
- Support ONFi 4.0 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 with operating frequency up to 533Mbps
- Support NV-DDR3 with operating frequency up to 800Mbps
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ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
- Support ONFi 4.1 IO Electrical Specification
- Support Legacy up to 50MHz
- Support NV-DDR2 up to 533Mbps
- Support NV-DDR3 up to 1200Mbps
