SafeSPI IP

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The Serial Peripheral Interface for Automotive Safety (SafeSPI) is an open standard based on the de-facto Serial Peripheral Interface (SPI) industry standard

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Compare 3 SafeSPI IP from 3 vendors (1 - 3)

SafeSPI Controller
- Compliant to SafeSPI Rev 2.0.
- Master, slave, or monitor roles
- All frame formats
- Slave selection options
SafeSPI Verification IP
- Supports 100% of SafeSPI protocol Standards.
- Supports bit encodings
- Supports all SPI Transfers as per the Specification
- Supports all SafeSPI Timing Standards.
xSPI/SPI Verification IP
- Compliant to SPI Specification 512Mbit(64Mbyte) 3.0V SPI FLASH MEMORY S25FL5122
- Compliant with JEDEC JESD251A expanded serial peripheral interface specification with the help of JEDEC JESD216D-01 SFDP specification.
- Supports connection to any SPI Memory and SPI Master IP communicating with a CYPRESS spi flash memory model.
- Supports configurable timing parameters and multi-slave configurations.