Power-On-Reset IP

Overview

Innosilicon Power-On-Reset (POR) IP provides reliable reset function for general applications. It is powered by analog supply and monitors digital supply.
It generates POR_OUT signal to reset the digital logic. The POR signal is set low if analog supply or digital supply falls below the threshold voltage, and will be set high if both of analog supply and digital supply exceed the threshold voltage.

Key Features

Area: 0.0106mm2 (49um * 216um)

Note: The area parameters are for reference only. Please refer to the final LEF file for the actual values.

Low power: 21uA current consumption
1.8V supply for analog and 0.75V supply for digital
Built-in low power bandgap reference
Typical 1.35V threshold for 1.8V supply
Typical 0.5V threshold for 0.75V supply

Benefits

Low power consumption
Fully customizable
Small area
Simple integration process
Available options include:

FPGA integration support
Chip level integration

Deliverables

Datasheet
Physical Integration Guide
Timing Library Model (LIB)
Encrypted Verilog Model
Library Exchange Format (LEF)
GDSII Database
Evaluation Board if Available

Technical Specifications

Foundry, Node

TSMC 40/28/22/16/12/6/5/4/3nm, Samsung 14/10/8nm, GF 55/28/22/14/12nm, SMIC 55/40/28/14nm, HLMC 40/28nm, UMC 28nm

GLOBALFOUNDRIES

In Production: 12nm , 14nm LPP , 22nm FDX , 28nm SLP
Silicon Proven: 55nm LPX

SMIC

In Production: 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+

Samsung

In Production: 14nm
Pre-Silicon: 8nm , 10nm

TSMC

In Production: 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP
Pre-Silicon: 4nm
Silicon Proven: 3nm , 5nm , 6nm

UMC

Pre-Silicon: 28nm HPC

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