32-bit SRAM/PROM Controller
Overview
The 8/32-bit PROM/SRAM Controller IP cores is an 8/32-bit PROM/SRAM/IO controller that interfaces external asynchronous SRAM, PROM and I/O to the AMBA AHB bus. The controller can handle 32-bit wide SRAM and I/O, and either 8- or 32-bit PROM
Key Features
- AMBA AHB interface
- Low area consumption
- Compatible with AMBA-2.0
Deliverables
- VHDL source code
- Synplify project file
- VHDL test bench
- Template design for LEON3 processor
- FPGA evaluation board (optional)
Technical Specifications
Foundry, Node
Any
Maturity
Production
Availability
Immediate