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Adder/Subtractor IP

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  • High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
    • Design Flexibility
    • Portability
    • Ease of programmability
    Block Diagram -- High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
  • Single precision, IEEE 754, floating point adder
    • Single-precision (32-bit) floating point addition and subtraction.
    • IEEE 754 compliant.
    • Full support for infinities, NaNs and denormals.
    • Rounding is to the nearest even number.
  • Multiply Adder
    • Supports twos complement-signed and unsigned operations
    • Supports multiplier inputs ranging from 1 to 52 bits unsigned or 2 to 53 bits signed and an add or subtract operand input ranging from 1 to 105 bits unsigned or 2 to 106 bits signed
    • Optional pipelined operation
  • Adder/Subtracter
    • Generates adder, subtracter and add/subtracter functions
    • Supports two’s complement-signed and unsigned operations
    • Supports fabric implementation inputs ranging from 1 to 256 bits wide
    • Supports DSP48 slice implementation with inputs up to 48 bits wide 
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