Introducing the CXL 3.X Specification

By Mahesh Natu
System and Software WG Co-Chair - CXL Consortium
Senior Principal Engineer and Director of Platform Architecture – Intel Corporation

Introduction
Agenda
Industry Trends and CXL 3.X Themes
CXL Specification Release Timeline
Industry Standards Converge
CXL 3.0: Doubles Bandwidth with Same Latency
CXL 3.X Features Progression
CXL Scales New Heights
CXL Fabrics
CXL 3.x Peer-to-peer Comms
CXL 3.X - Memory Pooling
CXL 3.0: Coherent Memory Sharing
CXL Trusted Security Protocol (TSP)
TSP Feature Progression
CXL 3.2 Specification
CXL Hot-Page Monitoring Unit (CHMU) for Memory Tiering
CHMU Overview
Compatibility with the PCIe® MMPT ECN
CXL 3.2 Enhances Event Record
CXL 3.2 Enhances functionality of CXL Memory Devices for OS and Application
CXL Specification Feature Summary
Compliance Updates
Summary
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Semiconductor IP