Memory Controller & PHY IP for TSMC

Compare 3 Memory Controller & PHY IP for TSMC from 2 vendors (1 - 3)

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SD/eMMC - TSMC 7FF, North/South Poly Orientation
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
SD/eMMC in TSMC (28nm, 16nm, 12nm, N7, N6)
- Compliant with eMMC5.1 and SD 6.0
- Supports 1.2/1.8V and 3.3V bus voltages and all the operating modes for SD 6.0 and eMMC5.1
- Supports 1.8V signaling for SD 6.0 host–low voltage signaling (LVS)
- Includes high speed IOs and DLL/delay lines to guarantee alignment between the application processor and memory device
Supporting ONFI 5.0, 4.2, 4.1, 4.0 and ONFI 3 - TSMC 7nm 7FF,FF+