Other for TSMC

Compare 7 Other for TSMC from 5 vendors (1 - 7)

Bi-Directional LVDS with LVCMOS
- Compliant with TIA/EIA-644 LVDS standard, also meets sub-LVDS
- Receiver compatible with HSCL levels for differential clock/data input
- LVDS transmitter and receiver have independent power control
- LVDS transmitter has adjustable output current level
HEVC/H.265, H.264 Multi format Dual-core Codec IP for 8K 60fps
- HEVC - Main/Main 10 Profile, Level 5.2 High-tier
- H.264 - High/High 10 Profile, Level 6.0
ITU G.711 compressor
- Compresses 16-bit linear PCM to 8 bit a-law or u-law logarithmic PCM.
- Compliant to the ITU G.711 standard.
- Purely combinational logic RTL implementation.
- Silicon proven in ASIC and FPGA technologies for a variety of applications.
ITU G.711 expander
- Expands 8 bit a-law or u-law logarithmic PCM to 13/14 bit linear PCM.
- Compliant to the ITU G.711 standard.
- Purely combinational logic RTL implementation.
- Silicon proven in ASIC and FPGA technologies for a variety of applications.
ISDB-T1, Segment Tuner (470-860MHz UHF)
- High Performance
- Configurable 3/4 wire controller
- Self calibrating and programmable filter corner frequencies
- 8 Bit electronically tunable tracking filter
MIPI D-PHY/sub-LVDS/CMOS1.8 combo Transmitter 2.5G/800Mbps 8-Lane
- MIPI DPHY v1-2 / MIPI CSI2 compliant
- Differential signal of almost CIS serial outputs support
- Xtal Input Clock Frequency Selectable: 24 - 72MHz
- Input Clock Frequency:
Wide-range LVDS Video Interface
- Wide pixel clock range: 9MHz to 190MHz (VGA to HDTV and QXGA at 60fps) = 60Mb/s to 1.33Gb/s (proven beyond 2Gb/s) -- far exceeding range of discrete interfaces
- Compatible with 18bit, 24bit, and 30bit balanced and unbalanced pixel data
- 2.5V or 3.3V I/O voltage operation
- Input levels compatible with EIA/TIA-644 LVDS, subLVDS, and larger amplitude OpenLDI standards