IP Catalog > Foundries > Samsung > Interface IP > Memory Interface IP > DDR IP > LPDDR4 IP > LPDDR4 PHY IP

LPDDR4 PHY IP for Samsung

Welcome to the ultimate LPDDR4 PHY IP for Samsung hub! Explore our vast directory of LPDDR4 PHY IP for Samsung
All offers in LPDDR4 PHY IP for Samsung
Filter
Filter

Login required.

Sign in

Search (12)
Compare 12 LPDDR4 PHY IP for Samsung from 1 vendors (1 - 10)
  • LPDDR4 multiPHY V2 - SS 8LPU
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - SS 8LPU
  • LPDDR4 multiPHY V2 - SS 8LPP for Automotive AEC-Q100 Grade 1
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - SS 8LPP for Automotive AEC-Q100 Grade 1
  • LPDDR4 multiPHY V2 - SS 8LPP
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - SS 8LPP
  • LPDDR4X multiPHY - SS 14LPP18
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4X multiPHY - SS 14LPP18
  • LPDDR4 multiPHY V2 - SS 14LPP
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - SS 14LPP
  • LPDDR4X multiPHY - SS 11LPP
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4X multiPHY - SS 11LPP
  • LPDDR4 multiPHY V2 - SS 11LPP
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - SS 11LPP
  • LPDDR4 multiPHY V2 - SS 10LPP
    • Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
    • Support for data rates up to 4,267 Mbps (process dependent)
    • Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
    • PHY independent, firmware-based training using an embedded calibration processor
    Block Diagram -- LPDDR4 multiPHY V2 - SS 10LPP
  • LPDDR5/4/4X PHY - SS 14LPU for Automotive AEC-Q100 Grade 1
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - SS 14LPU for Automotive AEC-Q100 Grade 1
  • LPDDR5X/5/4X PHY - SS SF4X
    • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
    • Support for data rates up to 8533 Mbps
    • Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5X/5/4X PHY - SS SF4X
×
Semiconductor IP