Wide-range LVDS Video Interface

Overview

Key Features

• Wide pixel clock range: 9MHz to 190MHz (VGA to HDTV and QXGA at 60fps) = 60Mb/s to 1.33Gb/s (proven beyond 2Gb/s) -- far exceeding range of discrete interfaces
• Compatible with 18bit, 24bit, and 30bit balanced and unbalanced pixel data
• 2.5V or 3.3V I/O voltage operation
• Input levels compatible with EIA/TIA-644 LVDS, subLVDS, and larger amplitude OpenLDI standards
• Self-contained: Includes bandgap and PLL
• LOCK output indicates PLL is locked
• Includes RTL for Word alignment and Dynamic Phase alignment
• IO library integrated to simplify integration and lower ESD risk
• Trimmable on-die termination ensures excellent signal integrity
• Comprehensive power-down control
• Matching LVDS driver available
• Bi-directional variants also available

Deliverables

• GDSII
• CDL Netlist (MG Calibre Compatible)
• Functional Verilog Model
• Liberty timing models (.lib)
• LEF
• Application Note with integration and production test guidelines

Technical Specifications