The IGMSLRX01A is a synchronous, ultra-high density one port register file compiler. It is developed with TSMC 7 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process. Different combinations of words, bits, and column-selected number (MUX) can be used to generate the most desirable configurations.
By requesting the desired size and timing constraints, the IGMSLRX01A compiler is capable of providing suitable synchronous RAM layout instances within minutes. It can automatically generate the data sheets, Verilog behavioral simulation models, place & route models, and test patterns for use in ASIC designs. The duty cycle length can be neglected as long as the setup/hold times and minimum high/low pulse widths are satisfied. This allows a more flexible clock falling edge during each operation. Both the word write and the bit write mask operations are supported.
TSMC CLN7FF Synchronous One Port Register File Compiler
Overview
Key Features
- High Current One Port Register File operates within a voltage range from 0.675 V to 0.825 V and a junction temperature range from -40 oC to 125 oC. The available supported macro size is configured from 144 bits to 72K bits. The Compiler is divided into 3 groups according to their column-selected numbers (Mux=1, 2 or 4).
- Pins and metal layers
- 3 metal layers used
- Power mesh with M3 pins support
- Allow M3 channel routing through M3 power mesh
- Compilation option
- MUX selection for the desired macro aspect ratio
- Bit-write mask function (BWEB pin) that allows write to designated bits in a word
- Power management
- Sleep mode powers down most peripheral circuit for leakage reduction with data retention
- Deep sleep mode powers down the most of peripheral circuit for leakage reduction and retains memory array content with lower voltage
- Shut down mode achieves highest leakage reduction without data retention
- General
- High Current TSMC 6T 0.0342 um2 SRAM bit cell
- Frequently used EDA model support
Technical Specifications
Foundry, Node
TSMC 7nm CLN7FF
Maturity
Pre-silicon
TSMC
Pre-Silicon:
7nm
Related IPs
- Single Port Register File compiler - Memory optimized for high density and high speed - Dual voltage - compiler range up to 40 k
- Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- UMC 0.162um eFalsh/LL One Port Register File_x005F_x000D_ memory compiler
- TSMC CLN6FF Asynchronous Read Two Port Register File Compiler
- TSMC CLN16FFC Ultra High Density One Port Register File
- SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler